Application examples: adaptive filter. Application examples: adaptive filter. Application examples: adaptive filter * + Z -1

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1 Application-Domain-Specic Procesors Alreay covere: Architecture moel or processor moel. Retargetable coe generation. List scheuling. Toay s topics: -space exploration by example. Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 3 x filter c 0 c c 63 Control unit r - Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 4 Minimizes the ference between x an e reference signal y Many applications are possible echo cancelling for TV e flyback signal kwn without echoes automatic equalization of cables in ata transmission acoustic echo cancelling e x[n] x[n-] x[n-i] x[n-63] Z - Z - Z - x[n-i] A i mu t[n] c A 0 c 0 * A c * A i c i * A 63 n * * S 0 [n] S [n] S i [n] S 63 [n] ê [n] C i [n] * Z - t[n] C i [n-] Z - r[n] Selection/aaptation by: Sabih Gerez, University of Twente, April, e[n] Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 6

2 #efine mu 0. #efine WORD num<3, func main input, e : WORD r : WORD sum [ 0 ] WORD 0 x input t WORD * WORD mu i : :: en en ehat sum [ 64 ] r e ehat c[i]@ c [ i ] c [ i WORD t * i s [ i ] WORD i * c [ i sum [ i ] sum [ i ] s [ i ] Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 7 r w t * r x@i * sum[i] sum[i] RAM 66 clock cycles. mm ALU bus implementation ROM MULT Selection/aaptation by: Sabih Gerez, University of Twente, April, bus ACU implementation implementation RAM ALU ROM ACU RAM ACU ALU MULT RAM ROM ACU bus bus 50 clock cycles 0.7 mm 0 clock cycles.4 mm Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 9 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 0

3 Outline esign process retargetable coe generation problem statement ADSP/VLIW architectures Mistral /A RT esigner instructive emo Aelante application examples low power aspects Mistral /A RT esigner iscussion conclusion Mistral Mistral Estimation Low power aspects Architecture EXU ACTIVITY AREA POWER alu_ 0% 6 05 acs_asu_ 83% or_asu_ 0% 6 romctrl_ 6% 65 acu_ 36% ipb_ 0% opb_ % ctrl total area spee power Estimation Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 GSM viterbi ecoer : efault solution 3750 alu_ alu_ 96% 96% romctrl_ romctrl_48% 48% acu_ acu_ 6% 6% ipb_ ipb_ 5% 5% opb_ opb_ 3% 3% ctrl ctrl total total controller responsible for 70% of power consumption maximum resource-sharing heavy ecision-making : main loop with 6 metrics-computations per iteration EXU-numbers inclue Registers for local storage GSM viterbi ecoer : loop-foling alu_ alu_ 9% 9% romctrl_ romctrl_45% 45% acu_ acu_ 5% 5% ipb_ ipb_ 5% 5% opb_ opb_ % % ctrl ctrl total total area own by 33% power own by 35% 447 next step: reuce # of program-steps with secon ALU Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 3 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 4

4 GSM viterbi ecoer : ALU s GSM viterbi ecoer : x ACS-ASU cycle count own 30% area up 4% power own by 5% next step: introuce ASU to reuce ALU-loa 9739 alu_ alu_ 69% 69% alu_ alu_ 65% 65% romctrl_ romctrl_67% 67% acu_ acu_ 37% 37% ipb_ ipb_ 8% 8% opb_ opb_ 33% 33% ctrl ctrl total total func func ACS ACS M, M, M, M, MS, MS, MS MS M M M- M- M M M- M- fi; fi; M- M- M M M- M- M M fi; fi; en; en; EXU EXU ACTIV ACTIV AREA AREA POWER POWER alu_ alu_ 0% 0% acs_asu_ acs_asu_ 83% 83% or_asu_ or_asu_ 0% 0% romctrl_ romctrl_ 6% 6% acu_ acu_ 36% 36% ipb_ ipb_ 0% 0% opb_ opb_ % % ctrl ctrl total total cycle count own 5X power own 0X! Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 5 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 6 GSM viterbi ecoer : 4 x ACS-ASU alu_ alu_ 94% 94% acs_asu_ acs_asu_ 95% 95% acs_asu_ acs_asu_ 95% 95% acs_asu_3 acs_asu_3 95% 95% acs_asu_4 acs_asu_4 95% 95% split_asu_ split_asu_ 47% 47% or_asu_ or_asu_ 47% 47% romctrl_ romctrl_ 8% 8% acu_ acu_ 98% 98% ipb_ ipb_ 3% 3% opb_ opb_ 50% 50% ctrl ctrl total total cycle count own ather 5X area up 3% power own ather 3X! GSM viterbi example : summary Mistral power area cycles 7x 7x!! efault loop ALU ACS 4 ACS Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 7 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 8

5 applications Discussion: phase 3 SW coe generation yes OK? yes more appl.? HW esign Exploration phase processormoel Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 9 Freeze processor moel applications SW coe generation OK? yes Application software evelopment: constraint riven compilation Discussion: problems with VLIWs coe size an instruction banwith coe compaction reuce coe size after scheuling possible compaction ratio? e.g. p0 0.9 an p 0. information content entropy - p i log p i 0.47 maximum compression factor control parallelism uring scheuling switch between ferent processor moels 0% of coe 90% runtime architecture reuce number of control bits for operan aresses e.g. 8 reg TM 8 bits/issue slot for aresses only use stacks an fos Selection/aaptation by: Sabih Gerez, University of Twente, April, Discussion: clustere VLIW architectures RF RF RF3 RF4 FU FU FU3 FU4 RF RF RF3 RF4 flags FU FU FU3 FU4 IR IR IR3 IR4 Instruction memory Control Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 3 Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 3

6 Conclusions ADSPs provie efficient solutions for a well-efine application omain orers of magnitue higher efficiency. The methoology is interesting for IP creation. The key problem is retargetable compilation. A istribute VLIW moel is a goo compromise between HW an SW. Although an automatic process can generate a efault solution, the process usually is interactive an iterative for efficiency reasons. The key is fast an accurate feeback. Selection/aaptation by: Sabih Gerez, University of Twente, April, 00 33