EECS 322 Computer Architecture

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EECS 322 Compter Architectre Instrctor: Francis G. Wolff wolff@eecs.cwr.

1 EECS 322 Compter Architectre Instrctor: Francis G. Wolff Case Western Reserve University This presentation ses powerpoint animation: please viewshow Finite State achines CWRU EECS 38

2 Review: Single-Cycle Datapath 2 adders: PC+4 adder, Branch/Jmp offset adder PC 4 address Add memory RegDst Reg Sign 32 etend Shift left 2 ALUSrc 3 Add Reslt ALUctl Zero ALU ALU reslt Address em Data memory And em Branch emtoreg Harvard Architectre: Separate instrction and memory CWRU EECS 38

3 lti-cycle Processor Datapath Combine adders: add ½ & 3 temp. s, A, B, ALUOt Combine emory: add & 2 temp. s, IR, DR IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] [5 ] 2 Registers 2 A B Zero ALU ALU reslt ALUOt emory 6 Sign etend 32 Shift left 2 ALU control emtoreg [5 ] ALUSrcB ALUOp Single-cycle= ALU + 2 em + 4 es + 2 adders + OpcodeDecoders lti-cycle = ALU + em + 5½ es + 5 Reg (IR,A,B,DR,ALUOt) + FS CWRU EECS 38

4 lti-cycle Datapath: with FS controller PC Address emory emdata [3-26] [25 2] [2 6] [5 ] [5 ] emory PCCond PC IorD em em emtoreg IR [25 ] [5 ] Otpts Control Op [5 ] PCSorce ALUOp ALUSrcB ALUSrcA RegDst 6 Reg 2 Registers Sign etend 2 32 Shift left 2 A B Shift 28 left 2 ALU control PC [3-28] Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] New path controls: IorD, ALUSrcA, PC Changed: ALUSrcB(was ALUsrc), PCCond(Branch), PCSorce CWRU EECS 38

5 CPU controller: Finite State achine ALUzero PCEnable PCCond PCSorce PC ALUOp em ALUSrcA em ALUSrcB IorD FS Reg IR RegDst emtoreg Clock Reset IRopcode CWRU EECS 38

6 lti-cycle sing Finite State achine Finite State achine ( hardwired control ) Combinational control logic Datapath control otpts Otpts Inpts Inpts from IR[3-26] opcode and IR[5-] fnct fields State Net State Clock, on rising edge, latch in net state Cycle Cycle 2 Cycle 3 Cycle 4 CWRU EECS 38

7 Finite State achine: program overview T Fetch T 2 Decode T 3 Rformat BEQ JUP em T 4 Rformat+ LW2 SW2 T 5 LW2+ CWRU EECS 38

8 The For Stages of R-Format Cycle Cycle 2 Cycle 3 Cycle 4 R-Format Ifetch Reg/Dec Eec Wr Fetch: IR=E[$pc]; $pc=$pc+4; Fetch the instrction from the emory Decode: A=reg[$rs]; B=reg[$rt]; Datapath=(IR[3-26,5-]) Registers Fetch and Decode for path Eec: ALUOt = A Fnct B ALU operates on the two operands Update PC : Reg[$rd]=ALUOt the ALU otpt back to the file CWRU EECS 38

9 R-Format State achine Cycle Cycle 2 Cycle 3 Cycle 4 R-Format Ifetch Reg/Dec Eec Wr Clock= Decode Clock= Fetch Eec Clock= Clock= CWRU EECS 38

10 The Five Stages of Load Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Fetch: Reg/Dec Eec Decode: A=reg[$rs]; Datapath=(IR[3-26]) Registers Fetch and Decode for path Eec: em ALUot = sign_etend(offset) + A Calclate the memory address em: DR = em[aluot] the from the Data emory Wr: Load Ifetch IR=E[$pc]; $pc=$pc+4; Fetch the instrction from the emory Reg[$rt]=DR the back to the file Wr CWRU EECS 38

11 R-Format & I-Format State achine Need to to check instrction format Clock= Decode Clock= AND R-Format= Clock= AND I-Format= Fetch Eec ALU Eec Offset Clock= Clock= Reg Clock= Reg em Clock= Clock= AND opcode=lw Need to to check opcode CWRU EECS 38

12 lti- seqence Cycle lw: 5 clocks Cycle 2 Cycle 3 Cycle 4 Cycle 5 sw: 4 clocks Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Clk Load Ifetch Reg Eec em Wr Store Ifetch Reg Eec em R-type Ifetch CWRU EECS 38

13 State machine stepping: T Fetch (Done in parallel) IR EORY[PC] & PC PC + 4 IorD em em IR RegDst Reg ALUSrcA PC Address PC emory emdata [25 2] [2 6] IR [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

14 T Fetch: State machine Cycle Cycle 2 Cycle 3 Cycle 4 Start R-Format Ifetch Reg/Dec Eec Wr em=, em= IorD= (emaddr PC) IR= (IR em[pc]) ALUSrcA= (=PC) ALUSrcB= (=4) (=4) ALUOP=ADD (PC 4+PC) PC=, PCSorce= (=ALU) Reg=, emtoreg=, RegDst= Fetch Decode Reg Eec CWRU EECS 38

15 T 2 Decode (read $rs and $rt and offset+pc) A Reg[IR[25-2]] & B Reg[IR[2-6]] & ALUOt PC+signet(IR[5-]) <<2 PC IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata $rs $rt offset [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

16 T 2 Decode State machine Cycle Cycle 2 Cycle 3 Cycle 4 R-Format Ifetch Reg/Dec Eec Wr Start Fetch em=, em= IorD= IR= ALUSrcA= (=PC) ALUSrcB=3 (=signet(ir<<2)) ALUOP= (=add) PC=, PCSorce= Reg=, emtoreg=, RegDst= Instr. Decode & Register Fetch Reg Eec CWRU EECS 38

17 T 3 EecALU (ALU instrction) ALUOt A op(ir[3-26]) B IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg op(ir[3-26]) ALUSrcB ALUOp CWRU EECS 38

18 T 3 EecALU State machine Cycle Cycle 2 Cycle 3 Cycle 4 R-Format Ifetch Reg/Dec Eec Wr Start Decode R-Format Eection Fetch Reg em=, em= IorD= IR= ALUSrcA= (=A (=A =Reg[$rs]) ALUSrcB= (=B (=B =Reg[$rt]) ALUOP=2 (=IR[28-26]) PC=, PCSorce= Reg=, emtoreg=, RegDst= CWRU EECS 38

19 T 4 WrReg (ALU instrction) Reg[ IR[5-] ] ALUOt IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

20 T 4 WrReg State machine Cycle Cycle 2 Cycle 3 Cycle 4 Start R-Format Ifetch Reg/Dec Eec Wr Fetch Decode R-Format Register em=, em= IorD= IR= ALUSrcA= ALUSrcB= ALUOP= PC=, PCSorce= Reg=, (Reg[$rd] ALUot) emtoreg=, (=ALUot) RegDst= (=$rd) Eec CWRU EECS 38

21 Review oore achine Processor Control Lines em em IorD... IR[3-] Net State CWRU EECS 38

22 oore Otpt State Tables: O(State) State T T 2 T 3 -R T 4 -R em em U IorD =PC IR ALUOP =op U ALUSrcA =PC =PC =A =$rs U ALUSrcB =4 3 =offset =B =$rt PC U PCSorce =ALU Reg U emtoreg =ALUOt U RegDst =$rd CWRU EECS 38

23 Review: The Five Stages of Load Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch Reg/Dec Eec em Wr Fetch: Fetch the instrction from the emory Decode: Registers Fetch and Decode Eec: Offset Calclate the memory offset em: the from the Data emory Wr: the back to the file CWRU EECS 38

24 Review: R-Format & I-Format State achine Need to to check instrction format Clock= Decode Clock= AND R-Format= Clock= AND I-Format= Fetch Eec ALU Eec Offset Clock= Clock= Reg Clock= Reg em Clock= Clock= AND opcode=lw Need to to check opcode CWRU EECS 38

25 T 3 I em (common to both load & store) ALUOt IorD em em A + sign_etend(ir[5-]) IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

26 T 3 em I-Format State achine =$rs + offset Decode Clock= AND R-Format= Clock= AND I-Format= Fetch Reg Reg em Eec ALU Clock= AND opcode=lw em=, em= IorD= IR= ALUOP= + ALUSrcA= =A =A =Reg[$rs] ALUSrcB=2 =signet(ir[5-]) PC=, PCSorce= Reg=, emtoreg=, RegDst= I-Format Eection ALUot=$rs+offset CWRU EECS 38

27 T 4 LW : load instrction, read memory DR IorD em emory[aluot] em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

28 T 4 LW2 I-Format State achine =em[alu] Fetch Reg Decode Reg Clock= AND opcode=lw Clock= AND R-Format= Eec ALU Clock= AND I-Format= Eec Offset I-Format emory em=, em= IorD= IR= ALUOP= ALUSrcA= ALUSrcB= PC=, PCSorce= Reg=, emtoreg=, RegDst= Clock= AND opcode=lw CWRU EECS 38

29 T 5 LW2 Load instrction, write to Reg[ IR[2-6] ] DR IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

30 T 5 LW2 I-Format State achine $rt=dr Fetch Decode Reg Clock= AND R-Format= Eec ALU I-Format Register em=, em= IorD= IR= ALUOP= ALUSrcA= ALUSrcB= PC=, PCSorce= Reg=, emtoreg=, RegDst= Clock= AND I-Format= Eec Offset Clock= AND opcode=lw em Clock= AND opcode=lw CWRU EECS 38

31 T 4 SW2 Store instrction, write to memory emory[ ALUOt ] B IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

32 T 4 SW2 I-Format State achine em[alu]= Fetch Decode Reg Clock= AND R-Format= Eec ALU Clock= AND I-Format= Eec Offset Clock= AND opcode=sw I-Format emory em=, em= IorD= IR= ALUOP= ALUSrcA= ALUSrcB= PC=, PCSorce= Reg=, emtoreg=, RegDst= Store not Load! CWRU EECS 38

33 T 3 BEQ (Conditional branch instrction) If (A - B == ) { PC ALUOt; } IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero Zero ALU ALU reslt ALUOt ALUOt = Address compted in in T 2!! [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

34 T 3 BEQ I-Format State achine =$rs + offset Decode Clock= AND R-Format= Clock= AND opcode=branch Fetch Reg Eec ALU em=, em= IorD= IR= ALUOP= =sbtract ALUSrcA= =A =A =Reg[$rs] ALUSrcB= =B =B =Reg[$rt] PC=, PCCond=, PCSorce= =ALUot Reg=, emtoreg=, RegDst= B-Format Eection CWRU EECS 38

35 T 3 Jmp (Jmp Address) PC PC[3-28] IR[25-]<<2 IorD em em IR RegDst Reg ALUSrcA PC Address emory emdata [25 2] [2 6] [5 ] [5 ] emory [5 ] 6 2 Registers Sign etend 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt ALUOt [5 ] emtoreg ALUSrcB ALUOp CWRU EECS 38

36 oore Otpt State Tables: O(State) State T T 2 T 3 -R T 4 -R T 3 -I T 4 -SW T 4 -LW T 5 -LW em em U IorD =PC =ALU =ALU IR ALUOP =+ 2=op =add U ALUSrcA =PC =A=$rs =A=$rs U ALUSrcB =4 3 =B=$rt 2=sign PC U PCSorce =AL Reg U emtoreg =ALU =DR U RegDst =$rd =$rt CWRU EECS 38

37 lti-cycle: 5 eection steps T (a,lw,sw,beq,j) Fetch T 2 (a,lw,sw,beq,j) Decode and Register Fetch T 3 (a,lw,sw,beq,j) Eection, emory Address Calclation, or Branch Completion T 4 (a,lw,sw) T 5 (lw) emory Access or R-type instrction completion -back step INSTRUCTIONS TAKE FRO 3-5 CYCLES! CWRU EECS 38

38 lti-cycle Approach All operations in each clock cycle T i are done in parallel not seqential! For eample, T, IR = emory[pc] and PC=PC+4 are done simltaneosly! T T 2 T 3 T 4 T 5 Step name fetch decode/ fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then PC = PC [3-28] II comptation, branch/ (IR[5-]) PC = ALUOt (IR[25-]<<2) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR Between Clock T 2 and T 3 the microcode seqencer will do a dispatch CWRU EECS 38

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