2-1. Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Routability of FPGAs with Extremal Switch- Block Structures, IEICE Trans.

Transcription

1 Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Routability of FPGAs with Extremal Switch- Block Structures, IEICE Trans. on Fundamentals, Vol.E81-A, No.5, pp , Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Assignment of Intervals to Parallel Tracks with Minimun Total Cross-Talk, IEICE Trans. on Fundamentals, Vol.E81-A, No.9, pp , Yukiko Kubo, Yasuhiro Takashima, Sigetoshi Nakatake, and Yoji Kajitani, Self-reforming Steiner Trees by Flip and Applications to VLSI Interconnection, in Japanese, Trans. of IPSJ, Vol.41, No.5, pp , Ning Fu, Shigetoshi Nakatake,Yasuhiro Takashima, and Yoji Kajitani, Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, A Device- Level Placement with Schema Based Clusters in Analog IC Layouts, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake, A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Ning Fu, Shigetoshi Nakatake,Yasuhiro Takashima, and Yoji Kajitani, The Oct-Touched Tile: A New Architecture for Shape-Based Routing, IEICE Trans. on Fundamentals, Vol.E89-A, No.2, pp , Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani, A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os, IEICE Trans. on Fundamentals, Vol.E90-A, No.5, pp , Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura, A Relocation Method for Circuit Modifications, IEICE Trans. on Fundamentals, Vol.E90-A, No.12, pp ,

2 2-10. Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, Post-silicon Clock-timing Tuning Based on Statistical Estimation, IEICE Trans. on Fundamentals, Vol.E91-A, No.9, pp , Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi, Optimal Time-multiplexing in inter-fpga Connections for Accelerating Multi-FPGA Prototyping Systems, IEICE Trans. on Fundamentals, Vol.E91-A, No.12, pp , Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura, Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems, IPSJ Transactions on System LSI Design Methodology, Vol.3, pp.81 90, Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takahsima, An Effective Overlap Removable Objective for Analytical Placement, IEICE Trans. on Fundamentals, Vol.E96-A, No.6, pp , Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, and Shin ichi Wakabayashi, Inter-FPGA Routing for Partially Time-multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies, IEICE Trans. on Fundamentals, Vol.E98-A, No.12, pp , Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, and Yasuhiro Takashima, An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device, IEICE Trans. on Fundamentals, in Press Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Detailed-Routability of FPGAs with Extremal Switch-Block Structures, in Proc. of ED & TC 1996, pp , Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout, in Proc. of ASP-DAC 2000, pp.87 92, Yasuhiro Takashima, and Hiroshi Murata, SLASH: A Deterministic Block Placement Algorithm Based on Sequence-Pair, in Proc. of APC-CAS 2000, pp , Yasuhiro Takashima, and Hiroshi Murata, The Tight Upper Bound of the Empty Rooms in Floorplan, in Proc. of SASIMI 2001, pp , Yasuhiro Takashima, Akira Kaneko, Shinji Sato, and Mineo Kaneko, Two-Dimensional Placement Method Based on Divide-and-Replacement, in Proc. of APCCAS 2002, pp , Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani, Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints, in Proc. of ASP-DAC 2004, pp.19 24, Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts, in Proc. of ASP-DAC 2004, pp , Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, A Device- Level Placement with Multi-Directional Convex Clustering, in Proc. of GLSVLSI 2004, pp , Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake, A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, in Proc. of ISCAS 2

3 2004, Cgangwen Zhuang, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, An algorithm for checking slicing floorplan based on HPG and its application, in Proc. of ICCCAS 2004, pp , Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani, The Oct-Touched Tile: A New Architecture for Shape-Based Routing, in Proc. of GLSVLSI 2005, P1.13, Tan Yan, Qing Dong, Yasuhiro Takasima, and Yoji Kajitani, How Does Partitioning Matter for 3D Floorplanning?, in Proc. of GLSVLSI 2006, pp.73 78, Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani, A Performance-Driven Bipartitioning Algorithm for Multi-FPGA Implementation with Time-Multiplexed I/Os, in Proc. of FPT 2006, pp , Tan Yan, Shuting Li, Yasuhiro Takashima, and Hiroshi Murata, A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks, in Proc. of ASP-DAC 2007, pp , Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura, A Relocation Method for Circuit Modifications, in Proc. of MWSCAS 2007, pp , Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, A Novel Clock Deskew Method by Linear Programming, in Proc. of MWSCAS 2007, pp , Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, Post-Silicon Clock-timing Tuning Based on Statistical Estimation, in Proc. of SASIMI 2007, pp , Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi, ILP-Based Optimization of Time-Multiplexed I/O Assignment for Multi-FPGA Systems, in Proc. of ISCAS 2008, pp , Shuting Li, Tan Yan, Yasuhiro Takashima, and Hiroshi Murata, Fast Wire Length Estimation in Obstructive Block Placement, in Proc. of ICECS 2008, pp , Naoto Funatsu, and Yasuhiro Takashima, Overlap-aware Analytical Placement Based on Stable-LSE, in Proc. of SASIMI 2009, pp , Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura, Evaluation of Introducing Multiple Timemultiplexing Degrees to Inter-FPGA Connections on Multi-FPGA Systems, in Proc. of ITC-CSCC 2009, A , Masato Inagi, Yasuhiro Takashima, and Yuichi Nakamura, Globally Optimal Time-Multiplexing in Inter- FPGA Connections for Accelerating Multi-FPGA Systems, in Proc. of FPL 2009, pp , Takanobu Shiki, Yasuhiro Takashima, and Yuichi Nakamura, Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests, in Proc. of ISCAS 2010, pp , Masatomo Kuwano and Yasuhiro Takashima, Stable-LSE based Analytical Placement with Overlap Removable Length, in Proc. of SASIMI 2010, pp , (Outstanding Paper Award) Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takashima, An Effective Overlap Removable Objective for Analytical Placement, in Proc. of SASIMI 2012, pp , Seiya Nagatsuka and Yasuhiro Takashima, Sub-path delay estimation for reconvergent path, in Proc. of APCCAS 2012, pp ,

4 3-27. Tieyuan Pan and Yasuhiro Takashima, A Fixed-Length Routing Method Based on the Color-Coding Algorithm, in Proc. of SASIMI 2013, pp , Syota Kuwabara, Yukihide Kohira, and Yasuhiro Takashima, An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method, in Proc. of ASICON 2013, C5-3, Komei Nomura, Asuka Shinohara, Kazuo Teshima, and Yasuhiro Takashima, K.R.A.B. Blokusduo engine with High-level synthesis, HEART 2014 Design Contest: Blokus Duo, http: //lut.eee.u-ryukyu.ac.jp/dc14/, Masatsugu Hosoki, Seiya Nagatsuka, and Yasuhiro Takashima, Delay Estimation Method for Correlated Net Delay Variations, in Proc. of APCCAS 2014, pp , Tieyuan Pan and Yasuhiro Takashima, A Randomized Algorithm for the Fixed-Length Routing Problem, in Proc. of APCCAS 2014, pp , Yasuhiro Takashima, Takanobu Shiki, and Yuichi Nakamura, Statisitical Delay Estimation with Path- Delay Test, in Proc. of VMC 2010, Yasuhiro Takashima, Analytical Placement for Rectilinear Blocks, in Proc. of ASPDAC 2015, pp , item Yasuhiro Takashima, Shohei Mizutani, Kenji Hotta, Ryosuke Kohno, and Yuichi Nakamura, Application of Quadratic Placement Optimization to Proton Beam Therapy, in Proc. of TJCAS 2015, p. 18, ,,, FPGA, DA, pp , ,,, FPGA, 8, ,,,, 10, pp , ( ) ,, Sequence-Pair SLASH, 14 ( ), pp , ,,,, 2, 15 ( ), pp , Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, An ILP-Based Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, 16 ( ), pp , ,,,,, 4

5 21, pp , ,,,,, 22, pp , ,,, 24, pp , ,,, DA, ,,,,, DA, ,,,,, BSG,, CAS97-40(VLD97-40, DSP97-55), Vol.97, No.137(No.139, No.141), pp , ,,,,, (VLD98-22), vol.98, No.142, pp.53 60, ,,,, Flip, (VLD98-21), vol.98, No.142, pp.45 52, ,,, Simulated Quenching 2,, p.105, ,,,, Simulated Quenching 2, (VLD ), vol.100, No.646, pp.7 12, ,,, (VLD ), vol.101, No.646, pp , ,, Sequence-Pair, (VLD ), vol.101, No.467, pp , ,,,, 2, (VLD ), vol.101, No.694, pp. 1 8, ,,,, (VLD ), vol.102, No.683, pp , ,,,,,, (VLD ), vol.103, No.476, pp , ,,,,, IC, (VLD ), vol.103, No.476, pp , ,,, (VLD ), vol.106, pp.35 40,

6 ,,,, 2006, AS-1-6, ( ) ,,, I/O FPGA, (CAS ), vol.106, No., pp.13 17, ,,,, (CAS ), vol.106, No.567, pp.19 21, ,,,,, (VLD ), vol.106, No.549, pp.43 48, ,,,, (VLD ), vol.106, No.549, pp.67 72, ,,,, BGA, (VLD ), vol.106, No.549, pp.73 78, ,,,, (VLD ), vol.106, No.549, pp.85 90, ,,,, PDE, (VLD2007-9), vol.107, No.32, pp.13 18, (SLDM ) ,,,, (CAS ), vol.107, No.1, pp.55 60, Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals, (CAS ), pp. 7 12, Shuting Li, Tan Yan, Yasuhiro Takashima, and Hiroshi Murata, Fast Wire Length Estimation in Obstructive Block Placement, (VLD2008-8), pp. 7 12, ,,, LSE, (VLD ), pp , ,, Stable-LSE, (VLD ), pp , ,,,, I/O, (VLD ), pp , ,,,, (VLD ), pp , ,,,, (VLD ), pp , ,,, Stable-LSE 3, (VLD ), pp , ,, Stable-LSE, (VLD ), pp. 1 6, ,,,, (VLD ), pp ,

7 ,, Deskew, (VLD ), pp , ,,,, (VLD ), pp , ,,,, (VLD ), pp , ,,, CRP, (VLD ), pp , ,, CUDA, (VLD ), pp , ,,,, (VLD2011-2), pp. 7 12, ,, (VLD ), pp , ,,,, (VLD ), pp , ,,, 2011, A-3-7, ,,, 2011, A-3-18, ,,, (VLD ), pp , ,,, (VLD ), pp , ,,, (VLD2012-6), pp , ,, GPGPU, (VLD ), pp , ,,, APR Legalization, (VLD ), pp , ,, TSV, (VLD ), pp , ,, Rectilinear Block, (VLD ), pp , ,,,, (VLD ), pp , ,,,, (VLD ), pp , , Color-Coding, (VLD ), pp , , CUDA, (VLD ), pp. 7-12,

8 DA , (VLD ), pp , (MSS ), pp.31 34, [ ] (VLD ), p.71, Mate TRAX (RECONF ), pp , , K.R.A.B., 3 FPGA jp/ yoshiki/fpga/contest/index.php?fpga%c0%df%b7%d7%a5%b3%a5%f3%a5%c6%a5%b9%a5% C82013%20%A1%CABlokus%20Duo, Yasuhiro Takashima, K.R.A.B., ICFPT 2013 Design Competition: Blokus Duo, u-ryukyu.ac.jp/dc13/, Komei Nomura, Asuka Shinohara, Kazuo Teshima, and Yasuhiro Takashima, K.R.A.B. Blokusduo engine with High-level synthesis, HEART 2014 Design Contest: Blokus Duo, http: //lut.eee.u-ryukyu.ac.jp/dc14/, DA , K-Tra-X, 6, The 1st RECONF/CPSY/ARC/GI Trax, Takaaki Yahata, Saki Yamaguchi, Komei Nomura, and Yasuhiro Takashima, K-Tra-X, ICFPT 2015 Design Competition, 2015, ,, ,, ( ) ( ) 8

9 5 / ( ) LSI (3000 / ) NEDO & TLO ( ) ( ) LSI ( ) ( ) LSI NEC (2007, 2009, , , , , ) ( ) LSI NEC ( ) ( ) ( ) ( ) LSI ( ) ( ) VLSI , SASIMI 2010 Outstanding Paper Award, ASP-DAC 2015 TPC Vice chair. ASP-DAC 2013 TPC secretary, ASP-DAC 2014 TPC secretary. Advisory Member: Student Forum at ASP-DAC (2010, 2011). Co-Chair : IEICE/VLD Student Forum at ASP-DAC : IEICE Fundamentals Review ( ) : IEICE SoC (2013) : IEICE VLSI CAD (2008, 2009, 2010, 2011, 2012, 2013, 2014). : IEICE SoC (2014) OC Member : ICCCAS 2007, ASP-DAC (2009, 2011), SASIMI Technical Program Committee Member : ASP-DAC (2004, 2010, 2011, 2012), ICCAD (2014), SASIMI (2006, 2007, 2010, 2012, 2013, 2015), Student Forum at ASP-DAC 2008 : IEICE VLD IEICE CAS IPSJ SLDM (2012),

10 8,9,10 LSI. 2004, 2005, 2006, 2007, Session Chair : ASP-DAC (2003, 2009, 2010, 2011, 2012), SASIMI (2003, 2007, 2009, 2010), ICCCAS 2007, ICECS 2008, TENCON 2010, APCCAS 2014, ( 17, 20, 21 ), ( 24, 25 ), (2008), (2006, 2007), DA (2007, 2010, 2011), (2004, 2006), 10