NORMALIZED CV REGISTRATION NUM.: 00509

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1 - 1 NORMALIZED CV REGISTRATION NUM.: SURNAMES: Rossello Sanz NAME: Josep Lluis GENDER: **Home ID number: DATE OF BIRTH: 29/03/1973 Number of employee: A0506 Personal address: Antoni Lliteras, 10, 2ºB City: Palma POSTAL CODE: PHONE NUMBER: SPECIALIZATION (UNESCO CODES): Tecnologia electrònica (vegeu 2202, 2203, i 3325) ACADEMIC TRAINING Bachelors Degree Center Date Ciencias Físicas Universitat Illes Balears 06/1996 con grado Universitat Illes Balears 09/1998 Doctorate Center Date en Física Universitat Illes Balears 02/2002 THESIS DIRECTOR: Jaume Segura Fuster ACTUAL PROFESSIONAL SITUATION AND STARTING DATE: professor titular d escola univers. - 11/10/1999 ORGANIZATION: Universitat de les Illes Balears Center: Facultat de Ciències DEPT./SECT./STR. UNIT: Física POSTAL ADDRESS: Carretera de Valldemossa, km 7.5 ( Palma ) PHONE NUMBER (Add number and extension): ext CONTRACT TEMPLATE SCHOLARSHIP HOLDER TEMPORARY LEAVE OTHER SITUATION:... a) FULL TIME DEDICATION: b) PART TIME SPECIFY: PREVIOUS SCIENTIFIC OR TEACHING ACTIVITIES Activity Center/Institution Dates TEU Int. Universitat Illes Balears /2003 LANGUAGES WITH SCIENTIC INTEREST Language Speak Read Write **Anglès **Correctament **Correctament **Correctament DATE OF FULFILLMENT: 14/11/2005 SIGN:

2 **Publicacions en revistes - 2 Authors (signature): J. Segura, J. L. Roselló, J. Morra, H. Sigg Title: A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits Journal: IEEE Journal of Solid-State Circuits Volume: 33 Number: 8 Pages, Initial: 1262 final: 1265 Year: 1998 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 001 Authors (signature): J. L. Roselló, J. Segura Title: Charge-based analytical model for the evaluation of power consumption in sub-micron CMOS buffers Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 21 Number: 4 Pages, Initial: 433 final: 448 Year: 2002 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 002 Authors (signature): J. L. Roselló, J. Segura Title: Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis Journal: Electronics Letters Volume: 38 Number: 15 Pages, Initial: 772 final: 774 Year: 2002 Place of publication: (BULGARIA) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 003 Authors (signature): J. Altet, J. Rosselló, A. Rubio and J. Segura Title: Structural RFIC Testing through Built-in Thermal Monitoring Journal: IEEE Communications Magazine Volume: 41 Number: --- Pages, Initial: 98 final: 104 Year: 2003 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 004 Authors (signature): Roselló, J.; Segura, J. Title: An Analytical charge-based compact delay model for submicron CMOS inverters Journal: IEEE Transactions on Circuits and Systems I-Fundamental Theory and Applications Volume: 51 Number: 7 Pages, Initial: 1301 final: 1311 Year: 2004 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 005 Authors (signature): J.L. Rosselló and J. Segura Title: Accurate modelling of leakage currents in nanometre CMOS technologies Journal: Electronics Letters Volume: 41 Number: 3 Pages, Initial: 18 final: 19 Year: 2005 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 006 Authors (signature): J.L. Rosselló and J. Segura Title: A Compact Gate-Level Energy and Delay Model of Dynamic CMOS Gates Journal: IEEE Transactions on Circuits and Systems II-Analog and Digital Signal Processing Volume: --- Number: --- Pages, Initial: --- final: --- Year: 2005 Place of publication: (UNITED STATES) ISSN: --- Legal Deposit: --- Key: **Article article code: Order: 007

3 **Patents i Models d utilitat - 3 Inventor/s (signature): J. Segura, J. Rosselló, A. Keshavarzi, S. Narendra, V. De Title: Switched current source Application number: B1 First priority country: UNITED STATES Date of priority: 2003 Main institution: INTEL CORPORATION Countries you went: --- Institutions that are not using: --- Model: **Patent Patent code: Order: 001 Inventor/s (signature): José L. Rosselló Title: Circuito digital que implementa un algoritmo genético para la configuración de circuitos de propósito general Application number: P First priority country: SPAIN Date of priority: 2005 Main institution: UIB - Universitat de les Illes Balears Countries you went: --- Institutions that are not using: --- Model: **Patent Patent code: Order: 002

4 **Línies de recerca - 4 Line: Desenvolupament de models de consum a circuits CMOS submicrònics Center: Universitat de les Illes Balears Dates: /2002 Line: Desenvolupament de models de comportament térmic de circuits CMOS nanomètrics Center: Universitat de les Illes Balears Dates: /2005

5 **Tesis, tesines i treballs - 5 Title: Implementación en Circuitos de Lógica Programable de una Red Neuronal Autoconfigurable mediante Algoritmos Genéticos Ph.D. candidate: Marcos Garcia Chillón University: Universitat de les Illes Balears Faculty / School: Escola Politècnica Superior Year: 2005 Mark: **Excel lent Key: **Treball d Investigació Situation: **Autoria

6 **Presentació de comunicacions - 6 Authors: J. L. Roselló, E. Isern, M. Roca, E. García, J. Segura Title: An analytical model of the charge driven by CMOS buffers Conference: XII Design of Circuits and Integrated Systems Conference pp: Place of celebration: Sevilla (SPAIN) Year: 1997 code: Order: 001 Authors: I. de Paul, R. Picos, J. L. Rosselló, M. Roca, E. Isern, J. Segura, C. F. Hawkins Title: Transient current testing based on current (charge) integration Conference: International Workshop on IDDQ Testing Proceedings, pp: Place of celebration: San José, California (UNITED STATES) Year: 1998 code: Order: 002 Authors: J. L. Rosselló, E. Isern, M. Roca, J. Segura Title: An analytical model of CMOS buffers power consumption Conference: XIV Design of Circuits and Integrated Systems Conference pp: Place of celebration: Palma de Mallorca, (SPAIN) Year: 1999 code: Order: 003 Title: A physical modelation of the alpha-power law MOSFET model Conference: XV Design of Circuits and Integrated Systems Conference pp: Place of celebration: Le Corum, Montpellier (FRANCE) Year: 2000 code: Order: 004 Title: A simple power consumption model of CMOS buffers driving RC interconnect lines Conference: XI International Workshop on Power and Timing Modeling Place of celebration: Yverdon-Les-Bains (SWITZERLAND) Year: 2001 code: Order: 005 Title: Power-delay modeling of Dynamic CMOS gates for circuit optimization Conference: The International Conference on Computer Aided Design (ICCAD 01) pp: Place of celebration: San José, CA (UNITED STATES) Year: 2001 code: Order: 006 Title: Modelling the input-output coupling capacitor effects on the CMOS buffer power consumption Conference: XVI Conference on Design of Circuits and Integrated Systems pp: Place of celebration: Porto (PORTUGAL) Year: 2001 code: Order: 007

7 - 7 Title: A compact charge-based propagatiaon delay model for submicronic CMOS buffers Conference: XII International Workshop on Power and Timing Modeling (PATMOS 2002) pp: Place of celebration: Sevilla (SPAIN) Year: 2002 code: Order: 008 Title: A simple Analytical Description of Power Dissipation in Submicronic CMOS Buffers Conference: XVII Conference on Design of Circuits and Integrated Systems pp: Place of celebration: Santander (SPAIN) Year: 2002 code: Order: 009 Title: A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates Conference: XII International Workshop on Power and Timing Modeling (PATMOS 2003) Place of celebration: Torino (ITALY) Year: 2003 code: Order: 010 Authors: S.A. Bota, J.L. Rosselló, J.A. Segura Title: Standard-Cell Based Temperature Sensor for Deep Submicron CMOS technologies Conference: IX International Workshop on Thermal Investigations of Ics and systems,therminic V: 1, N: 1, pp: , D.L.:, ISBN: Place of celebration: Aix-en-Provence (FRANCE) Year: 2003 code: Order: 011 Authors: Rosselló, J.L.; Segura, J.A. Title: Power and Timing Modeling of Sub-micron CMOS Gates Kind of participation: **Poster Conference: Ph.D. Forum at the 40th Design Automation Conference (DAC03) Place of celebration: Anaheim (UNITED STATES) Year: 2003 code: Order: 012 Authors: J.L.Rosselló y J.A. Segura Title: A Physically-Based nth-power Law MOSFET Model for efficient CAD Implementation Conference: XVIII Design of Circuits and Integrated Systems Conference (DCIS03). Place of celebration: Ciudad Real (SPAIN) Year: 2003 code: Order: 013 Authors: Jaume Segura, J. L. Rosselló, S.A.Bota, Marcos Rosales y Carol de Benito Title: Low Temperature CMOS Design Kind of participation: **Poster Conference: 9th International Academic Forum Place of celebration: Barcelona (SPAIN) Year: 2004 code: Order: 014

8 - 8 Authors: J.L. Rosselló, Jaume Segura Title: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk Conference: Design Automation and Test in Europe (DATE 2004) Place of celebration: Paris (FRANCE) Year: 2004 code: Order: 015 Authors: S.A. Bota, M. Rosales, J.L. Rosello, A. Keshavarzi, J. Segura Title: WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW:A NEW TYPE OF DELAY-FAULT MECHANISM Conference: International Test Conference 2004 Proceedings of International Test Conference 2004, ISBN Place of celebration: Charlotte (UNITED STATES) Year: 2004 code: Order: 016 Authors: S.A. Bota, V. Canals, J.L. Rosello, J. Segura Title: RING-OSCILLATOR BASED TEMPERATURE SENSOR FOR DEEP SUBMICRON CMOS TECHNOLOGIES Conference: XIX Conference on Design of Circuits and Integrated Systems Proceedings of XIX COnference on Design of Circuits and Integrated Systems Place of celebration: Bordeaux (FRANCE) Year: 2004 code: Order: 017 Authors: J.L. Rosselló y J. Segura Title: Modeling the Influence of Clock Skew on Crosstalk Induced Delay in Submicron CMOS technologies Conference: XIX Design of Circuits and Integrated Systems Conference (DCIS04) Place of celebration: Burdeaux (FRANCE) Year: 2004 code: Order: 018 Authors: S.A. Bota, M. Rosales, J.L. Rosselló y J. Segura Title: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs Conference: Design, Automation and Test in Europe 2005 Place of celebration: Munich (GERMANY) Year: 2005 code: Order: 019 Authors: J.L. Rosselló, V. Canals, S.A. Bota, A. Keshavarzi y J. Segura Title: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs Conference: Design, Automation and Test in Europe 2005 Place of celebration: Munich (GERMANY) Year: 2005 code: Order: 020 Authors: Jose L Rossello, Jaume Segura Title: A Propagation Delay Model of Complex CMOS Gates Conference: Design of Circuits and Integrated Systems Conference 2005 Place of celebration: Lisboa (PORTUGAL) Year: 2005 code: Order: 021

9 - 9 Authors: Sebastià Bota, Josep Lluis Roselló, Marcos Rosales, Jaume Segura Title: Clock Skew Analysis Considering Intradie -Temperature Variations Conference: Design of Circuits and Integrated Systems Conference 2005 Place of celebration: Lisboa (PORTUGAL) Year: 2005 code: Order: 022 Authors: Jose L Rosselló, Sebastià Bota and Jaume Segura. Title: Compact Static Power Model of Complex CMOS Gates Conference: Int. Workshop on Power and Timing Modeling, Optimization and Simulation Place of celebration: Leuven (BELGIUM) Year: 2005 code: Order: 023 Authors: J.L. Rosselló, S.Bota, M. Rosales, J. Segura Title: THERMAL-AWARE DESIGN RULES FOR NANOMETER ICS Conference: Int. Workshop on Thermal Investigations of ICs and Systems Place of celebration: Belgirate (ITALY) Year: 2005 code: Order: 024 Authors: S. A. Bota,J. Segura, J. L. Rossello, M. Rosales Title: Temperature effects on circuit synchronism Conference: Microtechnologies for the new millenium VLSI Circuits and Systems II. Place of celebration: Belgirate (ITALY) Year: 2005 code: Order: 025

10 **Projectes Title of the project / contract: Técnicas avanzadas de verificación para circuitos digitales submicrónicos Kind of contract/program: TIC - Programa Nacional de Tecnologías de la Información y las Comunicaciones Financing Firm/administration: CICY - Comisión Interministerial de Ciencia y Tecnología (CICYT) Institutions participating: --- Number of the project / contract: TIC Amount: 0,00 Duration, since: 1998 Until: 2001 Main researcher: Jaume Agapit Segura Fuster Number of researchers participating: 7 Code of the project / contract: Order: 001 Title of the project / contract: Test multiparamétrico de circuitos microelectrónicos digitales y mixtos de altas prestaciones Kind of contract/program: TIC - Programa Nacional de Tecnologías de la Información y las Comunicaciones Financing Firm/administration: CICY - Comisión Interministerial de Ciencia y Tecnología (CICYT) Institutions participating: --- Number of the project / contract: TIC Amount: 0,00 Duration, since: 2002 Until: 2005 Main researcher: Jaume Agapit Segura Fuster Number of researchers participating: 6 Code of the project / contract: Order: 002 Title of the project / contract: Circuit design for Low-temperature CMOS ICs Kind of contract/program: TIC - Programa Nacional de Tecnologías de la Información y las Comunicaciones Financing Firm/administration: INTEL CORPORATION Institutions participating: UIB - Universitat de les Illes Balears Number of the project / contract: --- Amount: 0,00 Duration, since: 2002 Until: 2005 Main researcher: Jaume Agapit Segura Fuster Number of researchers participating: 4 Code of the project / contract: Order: 003 Title of the project / contract: Development of new test strategies for RF CMOS integrated circuits Kind of contract/program: TIC - Programa Nacional de Tecnologías de la Información y las Comunicaciones Financing Firm/administration: CICY - Comisión Interministerial de Ciencia y Tecnología (CICYT) Institutions participating: --- Number of the project / contract: CICYT TIC Amount: 0,00 Duration, since: 2003 Until: 2006 Main researcher: Eugeni García Moreno Number of researchers participating: --- Code of the project / contract: Order: 004

11 **Altres Mèrits o aclariments ASISTENCIA A CURSOS Understanding the limits of semiconductor technology, Antonio Rubio (UPC), 4th Summer Course on Selcted Microelectronic Design & Test topics. Palma de Mallorca, Julio 2002 Low-Power/Low-Voltage (LP/LV) Analog Circuit Design Eric Vittoz, CSEM, Neuchatel. Switzerland. 4 th Summer Course on Selected Microelectronic Design, Design & Test topics. Palma de Mallorca, Julio Transistor and Circuit Challenges in Nanometric Technology Scaling Vivek De and Ali Keshavarzi, Intel Corporation, USA. 4th Summer Course on Selected Microelectronic Design & Test topics. Palma de Mallorca, Julio ASISTENCIA A CURSOS Understanding the limits of semiconductor technology, Antonio Rubio (UPC), 4th Summer Course on Selcted Microelectronic Design & Test topics. Palma de Mallorca, Julio 2002 Low-Power/Low-Voltage (LP/LV) Analog Circuit Design Eric Vittoz, CSEM, Neuchatel. Switzerland. 4 th Summer Course on Selected Microelectronic Design, Design & Test topics. Palma de Mallorca, Julio Transistor and Circuit Challenges in Nanometric Technology Scaling Vivek De and Ali Keshavarzi, Intel Corporation, USA. 4th Summer Course on Selected Microelectronic Design & Test topics. Palma de Mallorca, Julio Design and Test of Low Voltage CMOS Circuits Kaushik Roy, (Purdue Univ.) and Ali Keshav

CMP annual users meeting, 5 February 2015, Paris 1

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