Lecture Notes in Computer Science 9040

Lecture Notes in Computer Science 9040 Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University, Lancaster, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M. Kleinberg Cornell University, Ithaca, NY, USA Friedemann Mattern ETH Zürich, Zürich, Switzerland John C. Mitchell Stanford University, Stanford, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel C. Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen TU Dortmund University, Dortmund, Germany Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Gerhard Weikum Max Planck Institute for Informatics, Saarbrücken, Germany

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Kentaro Sano Dimitrios Soudris Michael Hübner Pedro C. Diniz (Eds.) Applied Reconfigurable Computing 11th International Symposium, ARC 2015 Bochum, Germany, April 13 17, 2015 Proceedings ABC

Editors Kentaro Sano Tohoku University Sendai Japan Dimitrios Soudris National Technical University of Athens Athens Greece Michael Hübner Ruhr-Universität Bochum Bochum Germany Pedro C. Diniz University of Southern California Marina del Rey California USA ISSN 0302-9743 ISSN 1611-3349 (electronic) Lecture Notes in Computer Science ISBN 978-3-319-16213-3 ISBN 978-3-319-16214-0 (ebook) DOI 10.1007/978-3-319-16214-0 Library of Congress Control Number: 2015934029 LNCS Sublibrary: SL1 Theoretical Computer Science and General Issues Springer Cham Heidelberg New York Dordrecht London c Springer International Publishing Switzerland 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer International Publishing AG Switzerland is part of Springer Science+Business Media (www.springer.com)

Preface Reconfigurable computing provides a wide range of opportunities to increase performance and energy efficiency by exploiting spatial/temporal and fine/coarse-grained parallelism with custom hardware structures for processing, movement, and storage of data. For the last several decades, reconfigurable devices such as FPGAs have evolved from a simple and small programmable logic device to a large-scale and fully programmable system-on-chip integrated with not only a huge number of programmable logic elements, but also various hard macros such as multipliers, memory blocks, standard I/O blocks, and strong microprocessors. Such devices are now one of the prominent actors in the semiconductor industry fabricated by a state-of-the-art silicon technology, while they were no more than supporting actors as glue logic in the 1980s. The capability and flexibility of the present reconfigurable devices are attracting application developers from new fields, e.g., big-data processing at data centers. This means that custom computing based on the reconfigurable technology is recently being recognized as important and effective measures to achieve efficient and/or high-performance computing in wider application domains spanning from highly specialized custom controllers to general-purpose high-end programmable computing systems. The new computing paradigm brought by reconfigurability increasingly requires researches and engineering challenges to connect capability of devices and technologies with real and profitable applications. The foremost challenges that we are still facing today include: appropriate architectures and structures to allow innovative hardware resources and their reconfigurability to be exploited for individual application, languages, and tools to enable highly productive design and implementation, and system-level platforms with standard abstractions to generalize reconfigurable computing. In particular, the productivity issue is considered a key for reconfigurable computing to be accepted by wider communities including software engineers. The International Applied Reconfigurable Computing (ARC) symposium series provides a forum for dissemination and discussion of ongoing research efforts in this transformative research area. The series of editions was first held in 2005 in Algarve, Portugal. The second edition of the symposium (ARC 2006) took place in Delft, The Netherlands during March 1 3, 2006, and was the first edition of the symposium to have selected papers published as a Springer LNCS (Lecture Notes in Computer Science) volume. Subsequent editions of the symposium have been held in Rio de Janeiro, Brazil (ARC 2007), London, UK (ARC 2008), Karlsruhe, Germany (ARC 2009), Bangkok, Thailand (ARC 2010), Belfast, UK (ARC 2011), Hong Kong, China (ARC 2012), Los Angeles, USA (ARC 2013), and Algarve, Portugal (ARC 2014). This LNCS volume includes the papers selected for the 11th edition of the symposium (ARC 2015), held in Bochum, Germany, during April 13 17, 2015. The symposium attracted a lot of very good papers, describing interesting work on reconfigurable computing-related subjects. A total of 85 papers were been submitted to the symposium from 22 countries: Germany (20), USA (10), Japan (10), Brazil (9), Greece (6),

VI Preface Canada (3), Iran (3), Portugal (3), China (3), India (2), France (2), Italy (2), Singapore (2), Egypt (2), Austria (1), Finland (1), The Netherlands (1), Nigeria (1), Norway (1), Pakistan (1), Spain (1), and Switzerland (1). Submitted papers were evaluated by at least three members of the Technical Program Committee. After careful selection, 23 papers were accepted as full papers (acceptance rate of 27.1%) for oral presentation and 20 as short papers (global acceptance rate of 50.6%) for poster presentation. We could organize a very interesting symposium program with those accepted papers, which constitute a representative overview of ongoing research efforts in reconfigurable computing, a rapidly evolving and maturing field. Several persons contributed to the success of the 2015 edition of the symposium. We would like to acknowledge the support of all the members of this year s symposium Steering and Program Committees in reviewing papers, in helping in the paper selection, and in giving valuable suggestions. Special thanks also to the additional researchers who contributed to the reviewing process, to all the authors who submitted papers to the symposium, and to all the symposium attendees. Last but not least, we are especially indebted to Mr. Alfred Hoffmann and Mrs. Anna Kramer from Springer for their support and work in publishing this book and to Jürgen Becker from the University of Karlsruhe for their strong support regarding the publication of the proceedings as part of the LNCS series. January 2015 Kentaro Sano Dimitrios Soudris

Organization The 2015 Applied Reconfigurable Computing Symposium (ARC 2015) was organized by the Ruhr-University Bochum (RUB) in Bochum, Germany. Organization Committee General Chairs Michael Hübner Pedro C. Diniz Program Chairs Kentaro Sano Dimitrios Soudris Finance Chair Maren Arndt Publicity Chair Ricardo Reis Web Chairs Farina Fabricius Daniela Horn Proceedings Chair Pedro C. Diniz Special Journal Edition Chairs Kentaro Sano Pedro C. Diniz Michael Hübner University of Southern California/Information Sciences Institute, USA Graduate School of Information Sciences, Tohoku University, Sendai, Japan National Technical University of Athens, Greece Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil University of Southern California/Information Sciences Institute, USA Graduate School of Information Sciences, Tohoku University, Sendai, Japan University of Southern California/Information Sciences Institute, USA

VIII Organization Local Arrangements Chairs Maren Arndt Horst Gass Steering Committee Hideharu Amano Keio University, Japan Jürgen Becker Karlsruhe Institute of Technology, Germany Mladen Berekovic Braunschweig University of Technology, Germany Koen Bertels Delft University of Technology, The Netherlands João M. P. Cardoso Faculdade de Engenharia da Universidade do Porto, Portugal George Constantinides Imperial College of Science, Technology and Medicine, UK Pedro C. Diniz University of Southern California/Information Sciences Institute, USA Philip H.W. Leong University of Sydney, Australia Katherine (Compton) Morrow University of Wisconsin-Madison, USA Walid Najjar University of California Riverside, USA Roger Woods The Queen s University of Belfast, UK In memory of Stamatis Vassiliadis Delft University of Technology, The Netherlands Program Committee Zack Backer Jürgen Becker Mladen Berekovic Koen Bertels Matthias Birk João Bispo Stephen Brown João Canas Ferreira João M. P. Cardoso Cyrille Chavet Ray Cheung Daniel Chillet Kiyoung Choi Paul Chow René Cumplido Florent de Dinechin Los Alamos National Laboratory, Los Alamos, USA Karlsruhe Institute of Technology, Germany Braunschweig University of Technology, Germany Delft University of Technology, The Netherlands Karlsruhe Institute of Technology, Germany Instituto Superior Técnico/Universidade Técnica de Lisboa, Portugal Altera and University of Toronto, Canada Faculdade de Engenharia da Universidade do Porto, Portugal Faculdade de Engenharia da Universidade do Porto, Portugal Université de Bretagne-Sud, France City University of Hong Kong, China Inria Rennes, France Seoul National University, South Korea University of Toronto, Canada National Institute for Astrophysics, Optics, and Electronics, Mexico INSA Lyon, France

Organization IX Steven Derrien Pedro C. Diniz António Ferrari Carlo Galuzzi Diana Göhringer Frank Hannig Jim Harkin Reiner Hartenstein Dominic Hillenbrand Christian Hochberger Michael Hübner Waqar Hussain Tomonori Izumi Ricardo Jacobi Krzysztof Kepa Andreas Koch Dimitrios Kritharidis Vianney Lapotre Philip H.W. Leong Gabriel M. Almeida Eduardo Marques Konstantinos Masselos Antonio Miele Takefumi Miyoshi Horácio Neto Smail Niar Seda O. Memik Monica M. Pereira Christian Pilato Thilo Pionteck Marco Platzner Dan Poznanovic Kyle Rupnow Kentaro Sano Marco D. Santambrogio Yukinori Sato Pete Sedcole Yuichiro Shibata Dimitrios Soudris Université de Rennes 1, France University of Southern California/Information Sciences Institute, USA Universidade de Aveiro, Portugal Delft University of Technology, The Netherlands Friedrich-Alexander University Erlangen-Nürnberg, Germany University of Ulster, Northern Ireland, UK Technische Universität Kaiserslautern, Germany Karlsruhe Institute of Technology, Germany Technische Universität Dresden, Germany Tampere University of Technology, Finland Ritsumeikan University, Japan Universidade de Brasília, Brazil Virginia Bioinformatics Institute, USA Technische Universität Darmstadt, Germany Intracom Telecom, Greece LIRMM-CNRS, Montpellier, France University of Sydney, Australia Leica Biosystems/Danaher, Germany University of São Paulo, Brazil Imperial College of Science, Technology and Medicine, UK Politecnico di Milano, Italy e-trees Inc., Japan Instituto Superior Técnico, Portugal University of Valenciennes, France Northwestern University, Illinois, USA University Federal do Rio Grande do Norte, Brazil Columbia University, USA University of Lübeck, Germany Universität Paderborn, Germany Cray Inc., USA Nanyang Technological University, Singapore Tohoku University, Sendai, Japan Politecnico di Milano, Italy Japan Advanced Institute of Science and Technology, Japan Celoxica, Paris, France Nagasaki University, Japan National Technical University of Athens, Greece

X Organization David Thomas Tim Todman Pedro Trancoso Chao Wang Markus Weinhardt Theerayod Wiangtong Yoshiki Yamaguchi Peter Zipf Imperial College of Science, Technology and Medicine, UK Imperial College of Science, Technology and Medicine, UK University of Cyprus, Cyprus University of Science and Technology of China, China Hochschule Osnabrück, Germany Mahanakorn University of Technology, Thailand University of Tsukuba, Japan Universität Kassel, Germany Additional Reviewers Andreas Agne Ihsen Alouani Jecel Assumpção Jr. Cristiano Bacelar de Oliveira Rico Backasch Mouna Baklouti Davide B. Bartolini Cristopher Blochwitz Anthony Brandon Jae Min Cho David de La Chevallerie Gianluca Durelli Andreas Engel Peter Figuli Philip Gottschling Adib Haron Jan Heisswolf Gerald Hempel Rainer Hoeckmann Matei Istoan Moritz Joseph Lukas Jung Jehangir Khan Kyounghoon Kim Jinho Lee Jinx Liu Charles Lo Thomas Marconi Universität Paderborn, Germany University of Valenciennes, France University of São Paulo, Brazil University of São Paulo, Brazil Technische Universität Dresden, Germany École Nationale d Ingnieurs de Sfax, Tunisia Politecnico di Milano, Italy Universität zu Lübeck, Germany Delft University of Technology, The Netherlands Seoul National University, South Korea Technische Universität Darmstadt, Germany Politecnico di Torino, Italy University of Basel, Switzerland Karlsruhe Institute of Technology, Germany Technische Universität Darmstadt, Germany Delft University of Technology, The Netherlands Karlsruhe Institute of Technology, Germany Technische Universität Dresden, Germany Osnabrück University of Applied Sciences, Germany Inria, France Universität zu Lübeck, Germany Technische Universität Darmstadt, Germany University of Valenciennes, France Seoul National University, South Korea Seoul National University, South Korea University of Ulster, Northern Ireland, UK University of Toronto, Canada Delft University of Technology, The Netherlands

Organization XI Fernando Martin del Campo Luiz Martins Joachim Meyer Alessandro A. Nacci Sancta Pandit Lazaros Papadopoulos Erinaldo Pereira Michael Raitza Simon Reder Guillaume Salagnac Shimpei Sato Ali Asgar Sohanghpurwala Hyunjik Song Florian Stock Berna Torun Erik Vermij Alex Weiss Tobias Wiersema Bartosz Wojciechowski Jianfeng Zhang University of Toronto, Canada Federal University of Uberlandia, Brazil Karlsruhe Institute of Technology, Germany Politecnico di Milano, Italy University of Toronto, Canada Democritus University of Thrace, Greece University of São Paulo, Brazil Technische Universität Dresden, Germany Karlsruhe Institute of Technology, Germany INSA-Lyon, France Japan Advanced Institute of Science and Technology, Japan Virginia Polytechnic Institute and State University, USA Seoul National University, South Korea Technische Universität Darmstadt, Germany Delft University of Technology, The Netherlands IBM Research, The Netherlands Accemic gmbh, Germany Universität Paderborn, Germany Wroclaw University of Technology, Poland University of Toronto, Canada

Contents Architecture and Modeling Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks...................................... 3 Thiago Baldissera Biazus and Mateus Beck Rutzig A Vector Caching Scheme for Streaming FPGA SpMV Accelerators...... 15 Yaman Umuroglu and Magnus Jahre Hierarchical Dynamic Power-Gating in FPGAs..................... 27 Rehan Ahmed, Steven J.E. Wilton, Peter Hallschmid, and Richard Klukas Tools and Compilers I Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation................... 41 Ian Graves, Adam Procter, William L. Harrison, Michela Becchi, and Gerard Allwein ArchHDL: A Novel Hardware RTL Design Environment in C++......... 53 Shimpei Sato and Kenji Kise Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA........................................ 65 Zaid Al-Khatib and Samar Abdi Systems and Applications I Preemptive Hardware Multitasking in ReconOS..................... 79 Markus Happe, Andreas Traber, and Ariane Keller A Fully Parallel Particle Filter Architecture for FPGAs................ 91 Fynn Schwiegelshohn, Eugen Ossovski, and Michael Hübner TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools..... 103 Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, and Jürgen Becker

XIV Contents Tools and Compilers II Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures................................ 117 Dionysios Diamantopoulos, S. Xydis, K. Siozios, and D. Soudris SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.............................. 129 Luca Sterpone and Boyang Du Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties................................................ 141 Philipp A. Hartmann, Kim Grüttner, and Wolfgang Nebel Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components...................... 153 Xerach Peña, Fernando Rincon, Julio Dondo, Julian Caba, and Juan Carlos Lopez Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays............................. 167 Michael Metzner, Jesus A. Lizarraga, and Christophe Bobda Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip....... 179 Philipp Gorski, Tim Wegner, and Dirk Timmermann Survey on Real-Time Network-on-Chip Architectures................. 191 Salma Hesham, Jens Rettkowski, Diana Göhringer, and Mohamed A. Abd El Ghany Cryptography Applications Efficient SR-Latch PUF...................................... 205 Bilal Habib, Jens-Peter Kaps, and Kris Gaj Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study.................... 217 Ekawat Homsirikamol and Kris Gaj Dual CLEFIA/AES Cipher Core on FPGA........................ 229 João Carlos Resende and Ricardo Chaves

Contents XV Systems and Applications II An Efficient and Flexible FPGA Implementation of a Face Detection System.......................................... 243 Hichem Ben Fekih, Ahmed Elhossini, and Ben Juurlink A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context............................. 255 Jens Rettkowski, Philipp Wehner, Marc Schülper, and Diana Göhringer A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank........ 267 Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, and Tsutomu Sasao The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs............................................. 280 Tobias Strauch Extended Abstracts (Posters) A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures.................................. 293 Anupam Chattopadhyay and Xiaolin Chen Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA.............................. 301 Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, and Anupam Chattopadhyay A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.................................. 311 Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, and Jürgen Becker Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures....................... 321 Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, and George Economakos Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects............... 331 Lucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda L. Kastensmidt, Giovanni Bruni, and Christopher Frost

XVI Contents Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments.................................... 339 Paulo Matias, Rafael T. Guariento, Lirio O.B. de Almeida, and Jan F.W. Slaets DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems..................................... 349 Ren Chen and Viktor K. Prasanna Acceleration of Data Streaming Classification using Reconfigurable Technology.............................................. 357 Pavlos Giakoumakis, Grigorios Chrysos, Apostolos Dollas, and Ioannis Papaefstathiou On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach..................... 365 Tobias Wiersema, Sen Wu, and Marco Platzner Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform...................................... 373 Mansureh S. Moghaddam, M. Balakrishnan, and Kolin Paul A Challenge of Portable and High-Speed FPGA Accelerator............ 383 Takuma Usui, Ryohei Kobayashi, and Kenji Kise Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array................................... 393 Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, and Akifumi Ogiwara Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture.................... 401 Stephan Nolting, Guillermo Payá-Vayá, Florian Giesemann, and Holger Blume Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization................................. 411 Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, and Mohamed Abid DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost............................... 419 Ernesto Castillo, Gabriele Miorandi, Davide Bertozzi, and Wang Jiang Chau A Flexible Multilayer Perceptron Co-processor for FPGAs............. 427 Zeyad Aklah and David Andrews

Contents XVII Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs............................... 435 Maikon Bueno, Carlos R.P. Almeida, José A.M. de Holanda, and Eduardo Marques Towards Performance Modeling of 3D Memory Integrated FPGA Architectures............................................. 443 Shreyas G. Singapura, Anand Panangadan, and Viktor K. Prasanna Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL........................................... 451 Shinya Takamaeda-Yamazaki Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing................................. 463 Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, and Mitsuhisa Sato SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms.................................. 475 George Lentaris, Ioannis Stamoulias, Dionysios Diamantopoulos, Konstantinos Maragos, Kostas Siozios, Dimitrios Soudris, Marcos Aviles Rodrigalvarez, Manolis Lourakis, Xenophon Zabulis, Ioannis Kostavelis, Lazaros Nalpantidis, Evangelos Boukas, and Antonios Gasteratos Hardware Task Scheduling for Partially Reconfigurable FPGAs.......... 487 George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, and Dionisios Pnevmatikatos SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring.............. 499 Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris, and Leonidas Lymperopoulos Special Session 2: Horizon 2020 Funded Projects (Invited Papers) DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications... 513 Nele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno da Silva, Abdellah Touhafi, Alois Kern, Stephan Knappmann, Jens Rettkowski, Muhammed Soubhi Al Kadi, Diana Göhringer, and Michael Hübner

XVIII Contents Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective..................................... 519 Christos Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Diana Göhringer, Maria Dagioglou, Theodore Giannakopoulos, Stasinos Konstantopoulos, and Vangelis Karkaletsis Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach...................................... 531 Andreas Raptopoulos, Sotirios Xydis, and Dimitrios Soudris COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator............................................ 542 Ioannis Papaefstathiou, Gregory Chrysos, and Lambros Sarakis Author Index... 555