Detailed Table of Contents Foreword... xxi Preface...xxii Section 1 Design, Modeling and Verification Chapter 1 System-Level Design of NoC-Based Dependable Embedded Systems... 1 Mihkel Tagel, Tallinn University of Technology, Estonia Peeter Ellervee, Tallinn University of Technology, Estonia Gert Jervan, Tallinn University of Technology, Estonia Chapter 2 Synthesis of Flexible Fault-Tolerant Schedules for Embedded Systems with Soft and Hard Timing Constraints... 37 Viacheslav Izosimov, Semcon AB, Sweden Paul Pop, Technical University of Denmark, Denmark Petru Eles, Linköping University, Sweden Chapter 3 Optimizing Fault Tolerance for Multi-Processor System-on-Chip... 66 Dimitar Nikolov, Linköping University, Sweden Mikael Väyrynen, Linköping University, Sweden Urban Ingelsson, Linköping University, Sweden Virendra Singh, Indian Institute of Science, India
Chapter 4 Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams... 92 Artur Jutman, Tallinn University of Technology, Estonia Maksim Jenihhin, Tallinn University of Technology, Estonia Chapter 5 Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis...119 Daniel Große, University of Bremen, Germany Görschwin Fey, University of Bremen, Germany Rolf Drechsler, University of Bremen, Germany Section 2 Faults, Compensation and Repair Chapter 6 Advanced Technologies for Transient Faults Detection and Compensation... 132 Luca Sterpone, Politecnico di Torino, Italy Massimo Violante, Politecnico di Torino, Italy Chapter 7 Memory Testing and Self-Repair...155 Mária Fischerová, Institute of Informatics of the Slovak Academy of Sciences, Slovakia Elena Gramatová, Institute of Informatics of the Slovak Academy of Sciences, Slovakia Chapter 8 Fault-Tolerant and Fail-Safe Design Based on Reconfiguration... 175 Hana Kubatova, Czech Technical University in Prague, Czech Republic Pavel Kubalik, Czech Technical University in Prague, Czech Republic Chapter 9 Self-Repair Technology for Global Interconnects on SoCs... 195 Daniel Scheit, Brandenburg University of Technology Cottbus, Germany Chapter 10 Built-in Self Repair for Logic Structures... 216 Tobias Koal, Brandenburg University of Technology Cottbus, Germany
Chapter 11 Self-Repair by Program Reconfiguration in VLIW Processor Architectures... 241 Mario Schölzel, Brandenburg University of Technology Cottbus, Germany Pawel Pawlowski, Poznan University of Technology, Poland Adam Dabrowski, Poznan University of Technology, Poland Section 3 Fault Simulation and Fault Injection Chapter 12 Fault Simulation and Fault Injection Technology Based on SystemC... 268 Silvio Misera, Kjellberg Finsterwalde, Germany Roberto Urban, Brandenburg University of Technology Cottbus, Germany Chapter 13 High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis... 294 Urmas Repinski, Tallinn University of Technology, Estonia Maksim Jenihhin, Tallinn University of Technology, Estonia Anton Chepurov, Tallinn University of Technology, Estonia Chapter 14 High-Speed Logic Level Fault Simulation... 310 Sergei Devadze, Tallinn University of Technology, Estonia Section 4 Test Technology for Systems-on-Chip Chapter 15 Software-Based Self-Test of Embedded Microprocessors... 338 Paolo Bernardi, Politecnico di Torino, Italy Michelangelo Grosso, Politecnico di Torino, Italy Ernesto Sánchez, Politecnico di Torino, Italy
Chapter 16 SoC Self Test Based on a Test-Processor... 360 Tobias Koal, Brandenburg University of Technology Cottbus, Germany Rene Kothe, Brandenburg University of Technology Cottbus, Germany Chapter 17 Delay Faults Testing... 377 Marcel Baláž, Institute of Informatics of the Slovak Academy of Sciences, Slovakia Roland Dobai, Institute of Informatics of the Slovak Academy of Sciences, Slovakia Elena Gramatová, Institute of Informatics of the Slovak Academy of Sciences, Slovakia Chapter 18 Low Power Testing... 395 Zdeněk Kotásek, Brno University of Technology, Czech Republic Jaroslav Škarvada, Brno University of Technology, Czech Republic Chapter 19 Thermal-Aware SoC Test Scheduling... 413 Zhiyuan He, Linköping University, Sweden Petru Eles, Linköping University, Sweden Section 5 Test Planning, Compression and Compaction in SoCs Chapter 20 Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs... 434 Anders Larsson, Linköping University, Sweden Urban Ingelsson, Linköping University, Sweden Krishnendu Chakrabarty, Duke University, USA Chapter 21 Reduction of the Transferred Test Data Amount... 460 Ondřej Novák, Technical University Liberec, Czech Republic
Chapter 22 Sequential Test Set Compaction in LFSR Reseeding... 476 Artur Jutman, Tallinn University of Technology, Estonia Igor Aleksejev, Tallinn University of Technology, Estonia Compilation of References... 494 About the Contributors... 534 Index... 545