2-1. Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Routability of FPGAs with Extremal Switch- Block Structures, IEICE Trans.

Transcription

1 Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Routability of FPGAs with Extremal Switch- Block Structures, IEICE Trans. on Fundamentals, Vol.E81-A, No.5, pp , Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Assignment of Intervals to Parallel Tracks with Minimun Total Cross-Talk, IEICE Trans. on Fundamentals, Vol.E81-A, No.9, pp , Yukiko Kubo, Yasuhiro Takashima, Sigetoshi Nakatake, and Yoji Kajitani, Self-reforming Steiner Trees by Flip and Applications to VLSI Interconnection, in Japanese, Trans. of IPSJ, Vol.41, No.5, pp , Ning Fu, Shigetoshi Nakatake,Yasuhiro Takashima, and Yoji Kajitani, Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, A Device- Level Placement with Schema Based Clusters in Analog IC Layouts, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake, A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp , Ning Fu, Shigetoshi Nakatake,Yasuhiro Takashima, and Yoji Kajitani, The Oct-Touched Tile: A New Architecture for Shape-Based Routing, IEICE Trans. on Fundamentals, Vol.E89-A, No.2, pp , Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani, A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os, IEICE Trans. on Fundamentals, Vol.E90-A, No.5, pp , Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura, A Relocation Method for Circuit Modifications, IEICE Trans. on Fundamentals, Vol.E90-A, No.12, pp , Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, Post-silicon Clock-timing Tuning Based on Statistical Estimation, IEICE Trans. on Fundamentals, Vol.E91-A, No.9, pp ,

2 2-11. Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi, Optimal Time-multiplexing in inter-fpga Connections for Accelerating Multi-FPGA Prototyping Systems, IEICE Trans. on Fundamentals, Vol.E91-A, No.12, pp , Yasuhiro Takashima, Atsushi Takahashi, and Yoji Kajitani, Detailed-Routability of FPGAs with Extremal Switch-Block Structures, in Proc. of ED & TC 1996, pp , Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout, in Proc. of ASP-DAC 2000, pp.87 92, Yasuhiro Takashima, and Hiroshi Murata, SLASH: A Deterministic Block Placement Algorithm Based on Sequence-Pair, in Proc. of APC-CAS 2000, pp , Yasuhiro Takashima, and Hiroshi Murata, The Tight Upper Bound of the Empty Rooms in Floorplan, in Proc. of SASIMI 2001, pp , Yasuhiro Takashima, Akira Kaneko, Shinji Sato, and Mineo Kaneko, Two-Dimensional Placement Method Based on Divide-and-Replacement, in Proc. of APCCAS 2002, pp , Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani, Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints, in Proc. of ASP-DAC 2004, pp.19 24, Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts, in Proc. of ASP- DAC 2004, pp , Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, A Device-Level Placement with Multi-Directional Convex Clustering, in Proc. of GLSVLSI 2004, pp , Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, and Shigetoshi Nakatake, A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, in Proc. of ISCAS 2004, Cgangwen Zhuang, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, An algorithm for checking slicing floorplan based on HPG and its application, in Proc. of ICCCAS 2004, pp , Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, and Yoji Kajitani, The Oct-Touched Tile: A New Architecture for Shape-Based Routing, in Proc. of GLSVLSI 2005, P1.13, Tan Yan, Qing Dong, Yasuhiro Takasima, and Yoji Kajitani, How Does Partitioning Matter for 3D Floorplanning?, in Proc. of GLSVLSI 2006, pp.73 78, Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Yoji Kajitani, A Performance-Driven Bipartitioning Algorithm for Multi-FPGA Implementation with Time-Multiplexed I/Os, in Proc. of FPT 2006, pp , Tan Yan, Shuting Li, Yasuhiro Takashima, and Hiroshi Murata, A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks, in Proc. of ASP-DAC 2007, pp , 2

3 Kunihiko Yanagibashi, Yasuhiro Takashima, and Yuichi Nakamura, A Relocation Method for Circuit Modifications, in Proc. of MWSCAS 2007, pp , Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, A Novel Clock Deskew Method by Linear Programming, in Proc. of MWSCAS 2007, pp , Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, Post-Silicon Clock-timing Tuning Based on Statistical Estimation, in Proc. of SASIMI 2007, pp , Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, and Atsushi Takahashi, ILP-Based Optimization of Time-Multiplexed I/O Assignment for Multi-FPGA Systems, in Proc. of ISCAS 2008, pp , Shuting Li, Tan Yan, Yasuhiro Takashima, and Hiroshi Murata, Fast Wire Length Estimation in Obstructive Block Placement, in Proc. of ICECS 2008, pp , Naoto Funatsu, and Yasuhiro Takashima, Overlap-aware Analytical Placement Based on Stable-LSE, in Proc. of SASIMI 2009, pp , ,,, FPGA, DA, pp , ,,, FPGA, 8, ,,,, 10, pp , ,, Sequence-Pair SLASH, 14 ( ), pp , ,,,, 2, 15 ( ), pp , Yasuhiro Takashima, Shigetoshi Nakatake, and Yoji Kajitani, An ILP-Based Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects, 16 ( ), pp , ,,,,, 21, pp , ,,,,, BSG,, CAS97-40(VLD97-40, DSP97-55), Vol.97, No.137(No.139, No.141), pp ,

4 4-2-2.,,,,, (VLD98-22), vol.98, No.142, pp.53 60, ,,,, Flip, (VLD98-21), vol.98, No.142, pp.45 52, ,,, Simulated Quenching 2,, p.105, ,,,, Simulated Quenching 2, (VLD ), vol.100, No.646, pp.7 12, ,,, (VLD ), vol.101, No.646, pp , ,, Sequence-Pair, (VLD ), vol.101, No.467, pp , ,,,, 2, (VLD ), vol.101, No.694, pp. 1 8, ,,,, (VLD ), vol.102, No.683 pp , ,,,,,, (VLD ), vol.103, No.476, pp , ,,,,, IC, (VLD ), vol.103, No.476, pp , ,,, (VLD ), vol.106, No., pp.35 40, ,,,, 2006, AS-1-6, ( ) ,,, I/O FPGA, (CAS ), vol.106, No., pp.13 17, ,,,, (CAS ), vol.106, No.567, pp.19 21, ,,,,, (VLD ), vol.106, No.549, pp.43 48, ,,,, (VLD ), vol.106, No.549, pp.67 72, ,,,, BGA, (VLD ), vol.106, No.549, pp.73 78, ,,,, (VLD ), vol.106, No.549, pp.85 90, ,,,, PDE, (VLD2007-9), vol.107, No.32, pp.13 18, (SLDM 4

5 ) ,,,, (CAS2007l-28), vol.107, No.1, pp.55 60, Yuko Hashizume, Yasuhiro Takashima, and Yuichi Nakamura, A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals, (CAS ), pp. 7 12, Shuting Li, Tan Yan, Yasuhiro Takashima, and Hiroshi Murata, Fast Wire Length Estimation in Obstructive Block Placement, (VLD2008-8), pp. 7 12, ,,, LSE, (VLD ), pp , ,, Stable-LSE, (VLD ), pp , ,,,, I/O, (VLD ), pp , ,,, in press, ,,,, in press, ,, ,, ( ) ( ) 5 / ( ) LSI (3000 / ) NEDO & TLO ( ) ( ) LSI ( / ) ( ) LSI NEC ( /, / ) ( ) LSI 5

6 4.6 10, Co-Chair : IEICE/VLD Student Forum at ASP-DAC OC Member : ASP-DAC Technical Program Committee Member : ASP-DAC 2004, SASIMI 2006, SASIMI 2007, SASIMI 2009, Student Forum at ASP-DAC 2008,, ,9,10 LSI. 2004, 2005, 2006, 2007, Session Chair : ASP-DAC 2003, SASIMI 2003, SASIMI 2007, ICCCAS 2007, ICECS 2008, ASP-DAC 2009, ( 17, 20, 21 ), (2008), ( ), DA 2007, (2004, 2006), 6