Lecture Notes in Computer Science 4917

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1 Lecture Notes in Computer Science 4917 Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M. Kleinberg Cornell University, Ithaca, NY, USA Friedemann Mattern ETH Zurich, Switzerland John C. Mitchell Stanford University, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel Oscar Nierstrasz University of Bern, Switzerland C. Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen University of Dortmund, Germany Madhu Sudan Massachusetts Institute of Technology, MA, USA Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Moshe Y. Vardi Rice University, Houston, TX, USA Gerhard Weikum Max-Planck Institute of Computer Science, Saarbruecken, Germany

2 Per Stenström Michel Dubois Manolis Katevenis Rajiv Gupta Theo Ungerer (Eds.) High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008 Göteborg, Sweden, January 27-29, 2008 Proceedings 13

3 Volume Editors Per Stenström Chalmers University of Technology, Dept. of Computer Science and Engineering Gothenburg, Sweden Michel Dubois University of Southern California, Dept. of Electrical Engineering 3740 McClintock Ave., Los Angeles, CA , USA Manolis Katevenis FORTH-ICS 100 Plastira Ave., Vassilika Vouton, Heraklion, Crete, Greece Rajiv Gupta University of California, Riverside, Dept. of Computer Science and Engineering 408 Engineering Building II, Riverside, CA 92521, USA Theo Ungerer University of Augsburg, Institute of Computer Science Augsburg, Germany Library of Congress Control Number: CR Subject Classification (1998): B.2, C.1, D.3.4, B.5, C.2, D.4 LNCS Sublibrary: SL 1 Theoretical Computer Science and General Issues ISSN ISBN Springer Berlin Heidelberg New York ISBN Springer Berlin Heidelberg New York This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. Springer is a part of Springer Science+Business Media springer.com Springer-Verlag Berlin Heidelberg 2008 Printed in Germany Typesetting: Camera-ready by author, data conversion by Scientific Publishing Services, Chennai, India Printed on acid-free paper SPIN: /

4 Preface The first two editions of the HiPEAC conference series in Barcelona (2005) and Ghent (2007) have really demonstrated that the topics covered by HiPEAC attract a lot of interest. In the 2007 conference, about 200 people attended the conference and its satellite events. The third HiPEAC conference was held in Göteborg, the second largest city in Sweden. The offerings of this conference were rich and diverse. We offered attendees a set of four workshops on topics that are all central to the HiPEAC roadmap: multi-cores, compiler optimizations, reconfigurable computing, and interconnection networks. Additionally, a tutorial on the Sunflower Toolsuite was offered. The conference program was as rich as in the last years. It featured many important and timely topics such as multi-core processors, reconfigurable systems, compiler optimization, power-aware techniques and more. The conference also offered a keynote speech by Mateo Valero the Eckert-Mauchly Award winner in Several social events provided opportunities for interaction and exchange of ideas in informal settings such as a tour at the Universeum a science exhibition center and aquarium where the banquet took place as well. This year we received 77 submissions of which 14 papers were Committee papers. Papers were submitted from 22 different nations (about 40% from Europe, 25% from Asia, 30% from North America and 5% from South America), which is a token of the global visibility of the conference. We had the luxury of having a strong Program Committee consisting of 37 experts in all areas within the scope of the conference and we kept all reviewing within the Program Committee. Thus, each paper was typically reviewed by four Program Committee members. We collected 301 reviews and we were happy to note that each paper was rigorously reviewed before we made the decisions, despite the fact that we shortened the review phase and that reviewing took place during most reviewers precious vacation time. The Program Committee meeting was held in the center of Rome, the ancient capital of Italy. Despite a long trip for many members of the Program Committee, 16 PC members attended the meeting. For virtually all papers, at least two reviewers were present. The PC meeting was preceded by an discussion of papers among the reviewers. At the PC meeting the papers were discussed in the order of average score also including PC papers. When a paper was discussed where a participating PC member was either a co-author or had conflicts with that paper, that person left the room. We accepted 25 papers of which 4 are PC papers, yielding an acceptance rate of 32%. The end result of the whole effort was the high-quality program for the HiPEAC 2008 event. We hope that you learn and get much inspiration from this proceedings volume.

5 VI Preface The planning of a conference starts way ahead of the actual event. If it were not for the unselfish and hard work of a large number of devoted individuals, this conference would not have been as successful as it was. Let us first thank the authors for their great contributions which constitute the core of the conference. We were very fortunate to collect a great team to power this event and would like to thank all of them: Mats Brorsson (KTH) for putting together an attractive pre-conference program; Ewa Wäingelin (Chalmers) for the enormous effort she invested in the local arrangement; Per Waborg (Chalmers) for a fantastic job in keeping the costs within budget and running the books; Mike O Boyle (Edinburgh) for timely publicity campaigns; Jörg Mische and Theo Ungerer (Augsburg) for the hard work in putting together the proceedings; Michiel Ronsee (Ghent) for administering the submission and review system; and finally Sylvie Detournay (Ghent) for administering the web. Thanks to all of you! Finally, we would also like to mention the support from the Sixth Framework Programme of the European Union, represented by project officers Mercè Griera i Fisa and Panagiotis Tsarchopoulos, for sponsoring the event and for the travel grants. October 2007 Per Stenström Michel Dubois Manolis Katevenis Rajiv Gupta

6 Organization Executive Committee General Co-chairs Program Committee Co-chairs Workshop/Tutorials Chair Local Arrangements Chair Finance Chair Publicity Chair Publications Chair Submissions Chair Web Chair Per Stenström Chalmers University of Technology, Sweden Michel Dubois University of Southern California, USA Manolis Katevenis University of Crete / FORTH, Greece Rajiv Gupta University of California, Riverside, USA Mats Brorsson KTH, Sweden Ewa Wäingelin Chalmers University of Technology, Sweden Per Waborg Chalmers University of Technology, Sweden Mike O Boyle University of Edinburgh, UK Theo Ungerer University of Augsburg, Germany Michiel Ronsse Ghent University, Belgium Sylvie Detournay Ghent University, Belgium Program Committee Angelos Bilas Mats Brorsson Koen De Bosschere Jack Davidson Marc Duranton Babak Falsafi Paolo Faraboschi Kristian Flautner Chris Gniady Wen-mei Hwu Paolo Ienne Norm Jouppi FORTH / University of Crete, Greece KTH, Sweden University of Ghent, Belgium University of Virginia, USA NXP Semiconductors, Netherlands Carnegie Mellon University, USA HP Labs, Spain ARM, UK University of Arizona, USA University of Illinois, USA EPFL, Switzerland HP Labs, USA

7 VIII Organization Mahmut Kandemir Stefanos Kaxiras Christos Kozyrakis Scott Mahlke Peter Marwedel Avi Mendelson Andreas Moshovos Mike O Boyle Kunle Olukotun Yunheung Paek Santosh Pande Yale Patt Alex Ramirez Lawrence Rauchwerger John Regehr Andre Seznec Guri Sohi Olivier Temam Josep Torrellas Mateo Valero David Whalley Sudhakar Yalamanchili Pennsylvania State University, USA University of Patras, Greece Stanford University, USA University of Michigan, USA University of Dortmund, Germany Intel, Israel University of Toronto, Canada Edinburgh University, UK Stanford University, USA Seoul National Universiry, Korea Georgia Institute of Technology, USA University of Texas at Austin, USA UPC / BSC, Spain Texas A&M University, USA University of Utah, USA INRIA, France University of Wisconsin, USA INRIA, France University of Illinois, USA UPC / BSC, Spain Florida State University, USA Georgia Institute of Technology, USA Steering Committee Mateo Valero Anant Agarwal Koen De Bosschere Mike O Boyle Brad Calder Rajiv Gupta Wen-meiW.Hwu Josep Llosa Margaret Martonosi Per Stenström Olivier Teman UPC / BSC, Spain MIT, USA Ghent University, Belgium University of Edinburgh, UK University of California, USA University of California, Riverside, USA UIUC,USA UPC, Spain Princenton University, USA Chalmers University of Technology, Sweden INRIA Futurs, France Reviewers Minwook Ahn Mauricio Alvarez Sara Baghsorkhi Mauro Bianco Angelos Bilas Mauricio Breternitz Jr. Mats Brorsson Felipe Cabarcas Francisco Cazorla Luis Ceze Bruce Childers Doosan Cho Michael Chu Romain Cledat Michele Co

8 Organization IX Albert Cohen Clark Coleman Adrian Cristal Jack Davidson Koen De Bosschere Marc Duranton Ayose Falcon Babak Falsafi Kevin Fan Paolo Faraboschi Kristian Flautner Grigori Fursin Chris Gniady Daniel Gracia-Perez Brian Greskamp Jason Hiser Wen-mei Hwu Paolo Ienne Daniel Jimenez Jose Joao Norm Jouppi Mahmut Kandemir Stefanos Kaxiras DaeHo Kim Hokyun Kim Wonsub Kim Yongjoo Kim Christos Kozyrakis Manjunath Kudlur Tushar Kumar Christopher Kung Chang Joo Lee Jongwon Lee Piotr Lesnicki Yue Li Yongmo Liang Danny Lynch Scott Mahlke Peter Marwedel Mojtaba Mehrara Avi Mendelson Rustam Miftakhutdinov Pablo Montesinos Miquel Moreto Andreas Moshovos Gilles Mouchard Veynu Narasiman Mike O Boyle Kunle Olukotun Daniel Ortega Yunheung Paek Alex Pajuelo Santosh Pande Ioannis Papadopoulos Hyunchul Park Sanghyun Park Yale Patt Androniki Pazarloglou Maikel Pennings Antoniu Pop Alex Ramirez Lawrence Rauchwerger John Regehr Christopher Rodrigues Shane Ryoo Esther Salami Fermin Sanchez Oliverio Santana Andre Seznec Tim Smith Guri Sohi Jaswanth Sreeram Santhosh Srinath Samuel Stone Karin Strauss M. Aater Suleman Gabriel Tanase Olivier Temam Nathan Thomas Abhishek Tiwari Josep Torrellas Sain-Zee Ueng Mateo Valero Javier Vera David Whalley Sudhakar Yalamanchili Sami Yehia Jonghee Youn Kun Zhang Hongtao Zhong

9 Table of Contents Invited Program Supercomputing for the Future, Supercomputing from the Past (Keynote)... 3 Mateo Valero and Jesús Labarta I Multithreaded and Multicore Processors MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing... 9 Kevin D. Kissell rmpi: Message Passing on Multicore Processors with On-Chip Interconnect James Psota and Anant Agarwal Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, and Dimitrios S. Nikolopoulos IIa Reconfigurable - ASIP BRAM-LUT Tradeoff on a Polymorphic DES Design Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, and Stamatis Vassiliadis Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, and Georgi Gaydadjiev Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael de Nil, and Jef Van Meerbergen IIb Compiler Optimizations Fast Bounds Checking Using Debug Register Tzi-cker Chiueh

10 XII Table of Contents Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis Stijn Eyerman, Lieven Eeckhout, and James E. Smith An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems Marco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, and Erven Rohou III Industrial Processors and Application Parallelization Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions Todd T. Hahn, Eric Stotzer, Dineel Sule, and Mike Asal Experiences with Parallelizing a Bio-informatics Program on the Cell BE Hans Vandierendonck, Sean Rul, Michiel Questier, and Koen De Bosschere Drug Design Issues on the Cell BE Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, and Daniel Jiménez-González IV Power-Aware Techniques Coffee: COmpiler Framework for Energy-Aware Exploration Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, and Diederik Verkest Integrated CPU Cache Power Management in Multiple Clock Domain Processors Nevine AbouGhazaleh, Bruce Childers, Daniel Mossé, and Rami Melhem Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation Maziar Goudarzi, Tohru Ishihara, and Hamid Noori V High-Performance Processors The Significance of Affectors and Affectees Correlations for Branch Prediction Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, and Marios Kleanthous

11 Table of Contents XIII Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator Patrick Akl and Andreas Moshovos LPA: A First Approach to the Loop Processor Architecture Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, and Mateo Valero VI Profiles: Collection and Analysis Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm Roy Levin, Ilan Newman, and Gadi Haber Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy Vincent M. Weaver and Sally A. McKee Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior Frederik Vandeputte and Lieven Eeckhout VII Optimizing Memory Performance MLP-Aware Dynamic Cache Partitioning Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture Subhradyuti Sarkar and Dean M. Tullsen Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory Chun-Chieh Lin and Chuen-Liang Chen Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache Yosi Ben Asher, Omer Boehm, Daniel Citron, Gadi Haber, Moshe Klausner, Roy Levin, and Yousef Shajrawi Author Index

Lecture Notes in Computer Science 4367

Lecture Notes in Computer Science 4367 Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University,